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BD6081GU,BD6081GVW
Technical Note
? Writing protocol
A register address is transferred by the next 1 byte that transferred the slave address and the write-in command. The 3rd
byte writes data in the internal register written in by the 2nd byte, and after 4th byte or, the increment of register address is
carried out automatically. However, when a register address turns into the last address (1Ah), it is set to 00h by the next
transmission. After the transmission end, the increment of the address is carried out.
S X X X X X X X 0 A A7 A6 A5 A4 A3 A2 A1 A0 A D7 D6 D5 D4 D3 D2 D1 D0 A
*1
*1
D7 D6 D5 D4 D3 D2 D1 D0 A P
slave address
R/W=0(write)
register address
DATA
register address
increment
DATA
register address
_
from master to slave
from slave to master
A=acknowledge(SDA LOW)
A=not acknowledge(SDA HIGH)
S=START condition
P=STOP condition
*1: Write Timing
● Timing diagram
SDA
t BUF
SCL
t LOW
t SU;DAT
t HD;STA
t HD;STA
t HD;DAT
t SU;STA
t SU;STO
S
t HIGH
Sr
P
S
● Electrical Characteristics(Unless otherwise specified, Ta=25 ℃ , VBAT=3.6V, VIO=1.8V)
Parameter Symbol
Standard-mode
Min. Typ. Max. Min.
Fast-mode
Typ. Max.
Unit
【 I 2 C BUS format 】
SCL clock frequency
LOW period of the SCL clock
HIGH period of the SCL clock
Hold time (repeated) START condition
After this period, the first clock is generated
f SCL
t LOW
t HIGH
t HD;STA
0 - 100 0
4.7 - - 1.3
4.0 - - 0.6
4.0 - - 0.6
-
-
-
-
400
-
-
-
kHz
μ s
μ s
μ s
Set-up time for a repeated START condition t SU;STA
4.7 - - 0.6
-
-
μ s
Data hold time
Data set-up time
Set-up time for STOP condition
Bus free time between a STOP
and START condition
t HD;DAT
t SU;DAT
t SU;STO
t BUF
0 - 3.45 0
250 - - 100
4.0 - - 0.6
4.7 - - 1.3
-
-
-
-
0.9
-
-
-
μ s
ns
μ s
μ s
www.rohm.com
? 2011 ROHM Co., Ltd. All rights reserved.
11/35
2011.04 - Rev.A
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